The memory order guarantee in a release consistency model means to guarantee the global visibility of data, that is, to guarantee completion of a process which is necessary for realizing consistency between data held by a shared memory and that by caches.
Specifically, in order to realize consistency between data held by a shared memory and that by caches (for example, in a multiprocessor system, no occurrence of inconsistency in data stored in a memory to and from which each processor writes and reads data, and the like), when a Store instruction to write data into the shared memory is executed, an invalidation request for requesting invalidation of the same data, as stored in the shared memory, is issued to the caches. By detecting a timing of completion of processing the issued invalidation request, the computer system concerned guarantees the global visibility.
Japanese Patent Application Laid-Open No. 2010-044599 discloses a memory order guarantee by means of a “Store Fence instruction” (hereafter, described as a StoreFence instruction) and a “Load Fence instruction” (hereafter, described as a LoadFence instruction). The StoreFence instruction is an instruction to designate a timing for providing synchronization of a Release side processor and an Acquire side processor. After the LoadFence instruction is issued, ordinality of data in the shared memory needs to be guaranteed. That is, consistency between the shared memory and the cache memories needs to be guaranteed.
Japanese Patent Application Laid-Open No. 2000-181891 discloses, in a multiprocessor system with a shared memory, a method for guaranteeing shared memory access order. The method does not need to cause execution of a subsequent Store instruction to wait with the purpose of guaranteeing the storing order.
In a release consistency model, there is no restriction on the processing order of cache invalidation requests. Accordingly, with respect to invalidation requests issued before a predetermined timing, a state where their processing has been entirely completed may be referred to as “memory order guarantee” or “guarantee of data ordinality”.
Execution of an invalidation process at an Acquire side processor having received a corresponding invalidation request from the shared memory needs to be prior to that of the LoadFence instruction. If the invalidation process is executed later than the LoadFence instruction, data is read not from the shared memory but from the cache memory inside the Acquire side processor. As a result, it becomes possible that the data ordinality cannot be guaranteed.
By the way, Japanese Patent Application Laid-Open No. 2010-044599 does not describe any condition for executing the StoreFence instruction (described as a Release instruction in Japanese Patent Application Laid-Open No. 2010-044599). It is described there, however, that the Release side processor detects completion of a Store instruction through an Ack (acknowledgement) from the memory, and notifies the Acquire side processor of it by writing a flag. The Acquire side processor reads the flag by a Load instruction, subsequently broadcasts a LoadFence instruction to the whole memory banks and receives a reply with respect to it, and thereby guarantees completion of the invalidation request. On receiving the LoadFence instruction, the memory sends the processors all invalidation requests due to preceding Store instructions, and subsequently sends the Acquire side processor a reply with respect to the LoadFence instruction. Accordingly, Japanese Patent Application Laid-Open No. 2010-044599 has the following problems. (a) It is possible that, at a memory bank, the LoadFence instruction waits for even an invalidation request essentially having no relation with the synchronization process. (b) It is possible that the LoadFence instruction and the invalidation requests place a load on the network between the processors and the memory, and this tendency becomes more remarkable with increasing the number of processors and that of memory banks.
Further, while Japanese Patent Application Laid-Open No. 2000-181891 performs a control not to allow a store request to overtake an invalidation request (purge request), it does not refer so far as to a timing of completion of processing the invalidation request.